![]() ![]() In real-address mode, the IDT is an array of 4-byte far pointers (2-byte code segment selector and a 2-byte instruction pointer), each of which point directly to a procedure in the selected segment. In protected mode, the IDT contains an array of 8-byte descriptors, each of which is an interrupt gate, trap gate, or task gate. The selected interrupt descriptor in turn contains a pointer to an interrupt or exception handler procedure. The vector specifies an interrupt descriptor in the interrupt descriptor table (IDT) that is, it provides index into the IDT. (This behavior supports the use of INT1 by hardware vendors performing hardware debug.) In contrast, the INT1 instruction can deliver a #DBĮven if the CPL is greater than the DPL of descriptor 1 in the IDT. (The return address is a far address consisting of the current values of the CS and EIP registers.) Returns from interrupt procedures are handled with the IRET instruction, which pops the EFLAGS information and return address from the stack.Įach of the INT n, INTO, and INT3 instructions generates a general-protection exception (#GP) if the CPL is greater than the DPL value in the selected gate descriptor in the IDT. The primary difference is that with the INT n instruction, the EFLAGS register is pushed onto the stack before the return address. The action of the INT n instruction (including the INTO, INT3, and INT1 instructions) is similar to that of a far call made with the CALL instruction. Intel and Microsoft assemblers will not generate the CD03 opcode from any mnemonic, but this opcode can be created by direct numeric code definition or by self-modifying code.) (These features do not pertain to CD03, the “normal” 2-byte opcode for INT 3. The interrupt is always handled by a protected-mode handler. The interrupt redirection enabled by the virtual-8086 mode extensions (VME) does not occur.The interrupt is taken (without fault) with any IOPL value. The normal IOPL checks do not occur in virtual-8086 mode.The mnemonic ICEBP has also been used for the instruction with opcode F1.Īn interrupt generated by the INTO, INT3, or INT1 instruction differs from one generated by INT n in the following ways: For that reason, Intel recommends software vendors instead use the INT3 instruction for software breakpoints.ġ. 1 Hardware vendors may use the INT1 instruction for hardware debug. The INT1 instruction also uses a one-byte opcode (F1) and generates a debug exception (#DB) without setting any bits in DR6. (This one-byte form is useful because it can replace the first byte of any instruction at which a breakpoint is desired, including other one-byte instructions, without overwriting other instructions.) The INT3 instruction uses a one-byte opcode (CC) and is intended for calling the debug exception handler with a breakpoint exception (#BP). (The INTO instruction cannot be used in 64-bit mode.) The overflow interrupt checks the OF flag in the EFLAGS register and calls the overflow interrupt handler if the OF flag is set to 1. The INTO instruction is a special mnemonic for calling overflow exception (#OF), exception 4. The INT n instruction is the general mnemonic for executing a software-generated call to an interrupt handler. Some of these vectors are used for internally generated exceptions. The first 32 vectors are reserved by Intel for system use. Each vector provides an index to a gate descriptor in the IDT. The destination operand specifies a vector from 0 to 255, encoded as an 8-bit unsigned intermediate value. The INT n instruction generates a call to the interrupt or exception handler specified with the destination operand (see the section titled “Interrupts and Exceptions” in Chapter 6 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1). Generate overflow trap if overflow flag is 1. Generate software interrupt with vector specified by immediate byte.
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